Parallelizing power system contingency analysis using D programming language

TitleParallelizing power system contingency analysis using D programming language
Publication TypeConference Paper
Year of Publication2013
AuthorsSiddhartha Kumar Khaitan, James D McCalley
Conference Name2013 IEEE Power & Energy Society General Meeting
Date Published07/2013
Conference LocationVancouver, BC
KeywordsAA09-001, RTGRM, System Security Tools

To ensure security, analyzing a large number of contingencies is important, which requires use of parallel computing resources. In this paper, we present an approach for parallelization and load balancing of contingency analysis (CA) in power systems using D programming language. We parallelize CA using a multicore processor and and propose and employ work-stealing based efficient scheduling to achieve load-balancing. We evaluate the features of D which are important for parallelization of CA and obtaining large performance gains. Our approach promotes legacy code reuse and hence is suitable for modern control centers which cannot afford porting their legacy code to other high-performance computing (HPC) platforms. We have conducted time domain simulation using a large 13029-bus test system with hundreds of contingencies and parallelized CA over 2, 4, 8, 12 and 16 cores. The results have confirmed that our approach outperforms a conventional scheduling technique and also offers large computational savings over serial execution.